Methods of transmitting data between semiconductor devices through a transmission line include low voltage complimentary metal oxide semiconductor (LVCMOS) signaling and pseudo open drain (POD) signaling. FIG. 1A illustrates a memory system 10 using LVCMOS signaling. Referring to FIG. 1A, the memory system 10 includes a semiconductor memory device 11 such as a dynamic random access memory (DRAM), transmission lines 16 corresponding to data buses, and a memory controller 17.
The semiconductor memory device 11 may include a plurality of transceivers 12 and data input/output pads (or DQ pads) 15. Each of the transceivers 12 includes an output driver 13 and an input buffer 14. The memory controller 17 controls a data read operation and a data write operation of the semiconductor memory device 11. The memory controller 17 includes a plurality of transceivers 18 and DQ pads 21. Each of the transceivers 18 includes an output driver 19 and an input buffer 20.
The output driver 13 of the semiconductor memory device 11 may be an inverter type of driver including a PMOS transistor and an NMOS transistor or a buffer type of driver. The output driver 13 of the semiconductor memory device 11 drives the transmission line 16 having a characteristic impedance of 50 ohms, for example, with a power supply voltage VDDQ or a ground voltage VSSQ to transmit data to the input buffer 20 of the memory controller 17.
The output driver 19 of the memory controller 17 may be an inverter type of driver including a PMOS transistor and an NMOS transistor or a buffer type of driver. The output driver 19 of the memory controller 17 drives the transmission line 16 with the power supply voltage VDDQ or the ground voltage VSSQ to transmit data to the input buffer 14 of the semiconductor memory device 11.
In LVCMOS signaling, the voltage of the transmission line 16 varies between the power supply voltage VDDQ (a high level) and the ground voltage VSSQ (a low level). Accordingly, a data signal swing range in the transmission line 16 may be relatively large, and thus LVCMOS signaling may be used in a relatively low-frequency operation of the memory system 10. The low-frequency of the memory system 10 may be a frequency lower than about 300 MHz. When data is transmitted through the transmission line 16 according to LVCMOS signaling, there may be no direct current (DC) power component and only an alternating current (AC) power component may exist. Accordingly, LVCMOS signaling may provide relatively low power consumption.
FIG. 1B illustrates a memory system 20 using POD signaling. Referring to FIG. 1B, the memory system 20 may include a semiconductor memory device 21, transmission lines 27 corresponding to data buses, and a memory controller 28.
The semiconductor memory device 21 may be a graphic double data rate synchronous dynamic random access memory (DRAM). The semiconductor memory device 21 may include a plurality of transceivers 22 and DQ pads 26. Each of the transceivers 22 may include an output driver 23, a termination resistor RT1, a switch 24 and an input buffer 25. The termination resistor RT1 (having a terminal connected to the source of a power supply voltage VDDQ) and the switch 24 may provide an on die termination (ODT) circuit. The ODT circuit is a termination matching circuit that may reduce data distortion due to reflection of data transmitted through the transmission line 27. The ODT circuit may be activated when the switch 24 is turned on.
The memory controller 28 may control a data read operation and a data write operation of the semiconductor memory device 21. The memory controller 28 includes a plurality of transceivers 29 and DQ pads 33. Each of the transceivers 29 may include an output driver 30, a termination resistor RT2, a switch 31 and an input buffer 32. The termination resistor RT2 (having a terminal connected to the source of a power supply voltage VDDQ) and the switch 31 may provide an ODT circuit that is activated when the switch 31 is turned on.
The output driver 23 of the semiconductor memory device 21 may be an inverter type of driver including a PMOS transistor and an NMOS transistor or a buffer type of driver. The output driver 23 of the semiconductor memory device 21 may drive the transmission line 27 having a characteristic impedance of 50 ohm, for example, with the power supply voltage VDDQ or a ground voltage VSSQ to transmit data to the input buffer 32 of the memory controller 28. When data is transmitted to the input buffer 32 of the memory controller 28, the ODT circuit of the semiconductor memory device 21 may be inactivated and the ODT circuit of the memory controller 28 may be activated. Accordingly, when the NMOS transistor of the output driver 23 is turned on so that the transmission line 27 is maintained at a voltage higher than the ground voltage VSSQ (a low level), a standby current may flow through the activated ODT circuit of the memory controller 28, the transmission line 27, and the turned on NMOS transistor of the output driver 23 to generate DC power. That is, when the voltage of the transmission line 27 is low (when data on the transmission line 27 is “0”), DC power may be consumed.
The output driver 30 of the memory controller 28 may be an inverter type of driver including a PMOS transistor and an NMOS transistor or a buffer type of driver. The output driver 30 of the memory controller 28 may drive the transmission line 27 with the power supply voltage VDDQ or the ground voltage VSSQ to transmit data to the input buffer 25 of the semiconductor memory device 21. When data is transmitted to the input buffer 25 of the semiconductor memory device 21, the ODT circuit of the semiconductor memory device 21 may be activated and the ODT circuit of the memory controller 28 may be inactivated. Accordingly, when the NMOS transistor of the output driver 30 of the memory controller 28 is turned on so that the transmission line 27 is maintained at a voltage higher than the ground voltage VSSQ (a low level), a standby current may flow through the activated ODT circuit of the semiconductor memory device 21, the transmission line 27, and the turned on NMOS transistor of the output driver 30 of the memory controller 28 to consume DC power.
The voltage of the transmission line 27 may vary between the power supply voltage VDDQ (high level) and a voltage higher than the ground voltage VSSQ (low level) due to the ODT circuits of the of the semiconductor memory device 21 and the memory controller 28 in POD signaling. Thus, a data signal swing range in the transmission line 27 may be relatively small and the power supply voltage VDDQ may have relatively little overshoot and/or undershoot because of the ODT circuits of the semiconductor memory device 21 and the memory controller 28 in POD signaling. Accordingly, POD signaling may be used in a high-frequency operation of the memory system 20. The high-frequency of the memory system 20 may be a frequency greater than or equal to 300 MHz. When data is transmitted through the transmission line 27 using POD signaling, both a DC power component and an AC power component may exist, and thus POD signaling may consume relatively high power.
FIG. 2 is a table illustrating relationships between operating frequencies of the memory systems of FIGS. 1A and 1B and power consumed during LVCMOS signaling and POD signaling.
In the table of FIG. 2, AC power when data is transmitted through a single DQ pad may be calculated as follows.AC power=VDDQ2*C*F Here, VDDQ indicates a power supply voltage. C indicates a load capacitance at the side of the transmission line 27, viewed from an output driver of a semiconductor memory device of the memory system when data is transmitted from the semiconductor memory device to a memory controller of the memory system or a load capacitance at the side of the transmission line, viewed from an output driver of the memory controller when the data is transmitted from the memory controller to the semiconductor memory device. F indicates the operating frequency of the memory system.
In the table of FIG. 2, DC power when data is transmitted through a single DQ pad may be calculated as follows.DC power=VDDQ2/(RT+Ron)Here, VDDQ indicates a power supply voltage, RT indicates a termination resistance, and Ron indicates an on resistance of an NMOS transistor included in the output driver.
In FIG. 2, power is average power when data is transmitted through thirty-two DQ pads of the memory system at the power supply voltage VDDQ of 1.2V. Referring to FIG. 2, both a DC power component and an AC power component may exist in POD signaling and the DC power component may be a relatively large portion of the power consumed during POD signaling. A significant DC power component may not exist and substantially only an AC power component may exist in LVCMOS signaling.
A memory system included in a portable device such as a mobile phone may be required to consume relatively little power. Accordingly, the DC power component may be reduced in POD signaling and the AC power component may be reduced in LVCMOS signaling to decrease the power consumed by a memory system of a portable device.
Furthermore, LVCMOS signaling may be suitable for a low-frequency operation of a memory system while POD signaling may be suitable for a high-frequency operation of the memory system, as described above. Accordingly, a memory system capable of reducing power consumption and capable of being used for low-frequency and high-frequency operation may be needed.